The present invention relates generally to design automation, and relates more particularly to the at-speed structural test (ASST) of integrated circuit (IC) chips.
When IC chips come off the manufacturing line, the chips are tested “at-speed” to ensure that they perform correctly (and to filter out chips that do not perform correctly). In particular, the chips are tested at a specified voltage level (Vtest). In addition, the chips must meet a specified frequency level (Ftest) to be qualified as “good” chips.
The determination of Vtest and Ftest directly impacts the yield (i.e., the percentage of the chips that are shipped to customers) and the shipped product quality loss (i.e., the percentage of the chips that are shipped to customers that are “bad” chips). More stringent test conditions will improve shipped product quality loss but worsen yield. More relaxed test conditions will improve yield but worsen shipped product quality loss.
Conventionally, Vtest and Ftest are determined in a heuristic manner based on empirical hardware characterization. This approach is performed manually using engineering judgment. Thus, inherently, this approach has no mathematical formulation or statistical basis and requires significant human effort. The resulting test conditions are typically highly sensitive to variations in sample chips.